Forum Discussion
New ContributorPower analysis and assignment of I/O Pins
Hi Shriram,
Thank you for the clarification. However, Power Analyzer is to calculate the power consumption of the design, so the user can refer to which the highest power consumed by the design and work from that point to improve their design to get more power saving.
Additionally, you can refer to this forum thread where the user shares one technique to improve power saving for FPGA designs.
Power saving techniques for FPGA
You also can check this article What are the Power Saving values based on in the Cyclone V and Arria..
Regards,
Aqid
Regular ContributorHello Shriram,
I hope you have a good day.
Can I know on the details what do you mean by the parameters that define the power savings block? On top of that, would you also explain on the good and bad cases meaning when u mentioned on the assigning smart I/O pins?
Regards,
Aqid Ayman
shriram_INTLHello, Aqid.
With "what do you mean by the parameters that define the power savings block," I mean the Power Saving Summary in Quartus Prime Pro's compilation Report under the Power Analyzer section. Smart VID Power Savings and Power savings are shown here.
I'm wondering if there's a tuning option, such as a timing constraint, that can change the Power Saved statistic, or if it's all based on Verilog code.
Another point of view is Area vs. Power.
For example, I'm looking for I/O Pin assignment first, then erroneous I/O pins, because the number of pins (volts) versus area can result in better or lower power savings.Thanks and best regards,
Shriram
