'Post-map' matches 'rtl functional' but differs from 'post-fit'

After overthinking the problem, I agree, that the testbench generates a delta cycle between CLK rising edge and START assertion. It's apparently working in functional simualtion. But isn't the Active HDL post-fit simulation a timing simulation? In this case, it wouldn't be a problem of delta delays but timing violations related to the actual design timing. In other words, the real synthesized design, if exposing the same timing as the model, has the same problem.