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ModelSim or Quartus Simulator?
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It is ActiveHDL 7.2. But, I do nor remeber if I had any problems with either Xilinx or functional simulation.
if I define the small range counter
CNT: buffer integer range 0 to 1
the post-fit will not even compile because of
# Compile Error: Explicit type conversions are allowed between closely related types only.
at line
CNT <= IEEE.STD_LOGIC_ARITH.CONV_INTEGER(SIGNED(ww_CNT));
Range 0..2,
CNT: buffer integer range 0 to 2
compiles but crushes in simulation
RUNTIME Fatal Error: Value -2 out of range (0 to 2).
on the same line. Even the initial value
CNT: buffer integer range 0 to 2:= 0
does not change the things.
Where the negatives comes from? Either I do not understand something or there are more problems with Altera fitter than those related to delta delay. The RTL and post-synth still run somoothly.
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setting CLK and other input signals simultaneously doesn't create a valid timing
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Where do you see them changed simultaneously?
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