'Post-map' matches 'rtl functional' but differs from 'post-fit'

Here is an example. The synthesized counter first

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;   
entity BIST is
    port (         
        clk, start: std_logic;
        CNT: buffer integer range 0 to 1000
    );
end BIST;
    
architecture RTL of BIST is
        begin
            
            FF: process (CLK)
            begin
                
                if Rising_Edge(Clk) then              
                    
                    if CNT = 1000 then
                        CNT <= 0;
                    else
                        CNT <= CNT+1;
                    end if;
                    
                    if START='1' then
                        CNT <= 0;
                    end if;
                    
                end if;
        
            end process;
            
        
end RTL;        

and the verification test bench:

library IEEE, POST_SYNth_CUT;
use IEEE.STD_LOGIC_1164.ALL;  
entity VERIF_TB   is
end VERIF_TB  ;
architecture BEH of VERIF_TB  is
    signal CLK: std_logic; 
    constant PERIOD: TIME := 10 ns;
    signal START: std_logic;
    
begin
    
    
    FUNC: entity WORK.BIST
    port map(    
            CLK => CLK,
            START => START,
            CNT => open
    );
    PS: entity post_synth_CUT.BIST
    port map(
        CLK => CLK,
        START => START,
        CNT => open
    );
    
    CLOCK : process     
    begin
        CLK <= '0'; wait for 85*PERIOD/100;
        CLK <= '1';    wait for 15*PERIOD/100;
    end process;
    
    
    START_PROC: process
    begin 
        
        START <= '0';
        for cycle_cnt in 0 to 20 loop
            wait until CLK = '1';
        end loop;
        -- wait for 1 fs; -- add a delta dealy
        
        START <= '1';       -- pulse start
        wait until CLK = '1';
        
        START <= '0';
        wait;  
    end process;
    
    
end BEH;

On the 21th count (clock period), the start is made high. On the next clock, count is zero, therefore. But, it is not in the post-fit simulation.

The post-fit becomes 20->0 instead of taking value 21 as expected and as RTL and post-synthesis do. It seems that post-fit process, on clock edge, takes the start <= '1' that is raised after clock. It does not appear correct.

If TB delays the start by a moment then both counters are synchronous.

Is it because I use "9.1 Build 222 10/21/2009 SJ Web Edition" or Stratix II EP2S15F484C3? Simulator goes crazy?