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Without proper timing cionstraints it is not very likely that the design will work.
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I don't agree. Without timing constraints, the compiler will place and route the design in the easiest way and achieve a typical timing, as specified in the datasheet. Applying constraints, it can't do but modifying P&R within available limits. For a small chip as MAXII-240, there isn't much room to achieve large timing modifications at all.
The main purpose of timing constraints is to check the design implementation, which is generally meaningful of course. The present design, which is mostly using asynchronous flip flops and counters as far as I see, offers great opportunities for creating timing violations and unpredictable behaviour, I fear. To have it effectively checked in timing analysis, the timing of all input signals must be specified in timing constraints.
Although not impossible, it's no reasonable way to go, I think. Using a more synchronous design style is a better way to achieve predictable design behaviour.
P.S.: Unfortunately, it's difficult to guess, why the MAX II design doesn't work while a discrete implementation does. It may be due to the fact, that MAX II is considerably faster than e.g. standard HC logic, so it acts on small input glitches or ringing edges of level sensitive signals, that are ignored by those. Also ground bounce can be an issue. I don't see much alternatives to tracing the behaviour with an oscilloscope or logic analyzer and find out, where it fails.
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