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Hi,
I've been working on this project using a Max II w/ 240 macrocells. The program compiles without any error and the simulation gives expected results, yet when it is loaded onto the chip and tested, it does not work properly.
I'm trying to debug just one part of the program which is very simple. A computer sends various commands via a parallel port. Signals Address[0] and Data[3] are high while address[1-3] and Data[0-2] are low ( refer to the attached project file). On the rising edge of our clock or enable signal 'Strobe', the output 'Trig' is supposed to go high and stay high but in testing this did not happen.
After some debugging I saw that we had a problem with the demux that the Address bits are fed into. Looking further into it, I tested various combinations of the 4 Address bits (ie only using only A0 and A1 for example). Using only 1 Address signal worked, any combination of any 2 signals worked, a few of the combinations using 3 signals worked. The remaining combinations of 3 signals did not work as well as using all four.
I wanted to make sure I wasn't doing anything wrong logically, so I put together the same exact circuit logically using logic gate and flip flop ICs. This circuit worked perfectly yet the software which is supposed to do the same thing, did not.
Does anyone have any idea of what could be wrong? I am completely lost. I should also add I am using the web edition of Quartus v9
Thanks
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Hi,
I did not find any timing constraint ( fmax, input delay ...) in your project. Without proper
timing cionstraints it is not very likely that the design will work.
BTW: Your are using the default setting for unused pins, which is "Output driving Ground".
Make sure that this will not damage other devices. You can change the setting:
Assignments -> Settings -> Device -> Device and Pin Options -> Unused Pins
Kind regards
GPK
Honored Contributor
