Polynomial Evaluation

You wouldnt do divides like that, you can just append leading or trailing 0s, like Kaz suggested before the add, as long as you remember how many you need. The highest power is going to have the biggest effect though, and the smaller powers hardly any difference on the output (unless they are scaled by a large number).

I cant really be more specific about my coding point - I gave you a coded example. In VHDL, you do not need component declarations unless your code comes from another source (say Verilog, AHDL or a generated netlist). The entity declaration already has the ports listed, so by using direct instantiation you tell the compiler where to get the entity from. The problem with using a component is that you essentially have 2 copies of the same thing (component and entity) which means you need to maintain it in two places. If there is a missmatch, the compiler always assumes the component is correct, and then when it tries to map the component to the entity (which can be many minutes later during a compile) there is a missmatch and it will error. Using direct instatiation means it does the check right at the start.

--direct instantiation
some_entity_inst : entity some_library.some_entity
generic map (
....
)
port map (
...
);