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Take a step back. Before you start, think about how the circuit would look when created. Then go back and write the code.
The multiplier entity you have created will causes a massive bias by just removing the 16 LSBs. Did you intend to do this? and did you intend to floor your results (rather than round to nearest?)
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Dear Tricky,
I have a 16 bit DAC so I'm forced to remove the 16 LSBs.
Now I have created 7 multiplier with seven DFF with a generic delay. So that with the multipliers I can evaluate x^7, x^6, x^5...x^0 and, before the final sum (forgetting for now about the coefficients), I compensate the delays introduced by the multipliers with the DFFs.
In particular I think that x should be delayed 6 cycles in respect to x^7=((((x*x)*x)*x)*x)*x)*x, x^2 5 cycles and so on.
I have noticed that if I sum 8 signal of 16 bit at a time, I need a 24 bit output signal. By the way in VHDL seems that also the summing signals must be 24 bit. Now that I have 8 - 16 bit signals, there is a simple way on promoting them to 24 bit or I must create 8 new 24 bit signal and assignin them the 16 bit ones ?
Thank you for your time.
Honored Contributor
