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Steve4's avatar
Steve4
Icon for New Contributor rankNew Contributor
5 years ago
Solved

PLL Slave Ports

I'm building a MAX 10 design partially using platform designer. When I try to generate the PLL, additional avalon memory mapped slave ports are included. This is not something that's covered in th...
  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    5 years ago

    Hi Stephen Samarzia

    The PLL instantiated from Platform Designer consist of a wrapper for an ALTPLL IP core and Avalon-MM slave interface. You can export this signal if you need it or leave the signal unconnected.

    Alternatively, you can instantiate the ALTPLL IP through IP Catalog. The PLL generated with this won't have this signal generated.

    Thanks.

    Eng Wei

EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Stephen Samarzia

The PLL instantiated from Platform Designer consist of a wrapper for an ALTPLL IP core and Avalon-MM slave interface. You can export this signal if you need it or leave the signal unconnected.

Alternatively, you can instantiate the ALTPLL IP through IP Catalog. The PLL generated with this won't have this signal generated.

Thanks.

Eng Wei

EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Stephen Samarzia

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei