PLL is not consistently producing a clock

1) When its working, the 90mhz clock is easily measured on a resistor on the clock node. When I say the clock does not work, I mean there is no clock when it is probed with the scope. Instead of oscillating, it just sits at 3.3v.

This is a reference design, and once I had the clock/pll configuration I wanted, I left it alone. My main changes were just to the names of the plls and clocks, and not to the pin assignments or frequencies. I have been slowly adding additional pins and new components to this base design.

I will double-check, but I believe the resource report shows the same plls are being used with the same internal settings as it has always used.

2) I am using the classic timing. How do I generate the unconstrained paths report? I did not see any timing constraints in this reference design before I added the few I mentioned. What would constitute a minimal set of timing constraints for a project?

3) All the input clocks have assigned pins

4) This isn't using DDR. This is Altera's SDR core.