PLL is not consistently producing a clock

1) Please describe the difference between 90MHz working and no longer working? Does it come out a port and at other times stops? Does it come out but at the wrong frequency? Does the logic not work and you're not sure if it's the clock or not?

2) You've probably got a timing issue, something unconstrained that happens to make timing on some compiles and does not on others. Create an unconstrained paths report(I don't know if you're using the Classic Timing analyzer or TimeQuest, but you can do it with both)

3) Another possibility is a bad pin assignment. If an input clock pin isn't assigned, then on some compiles the fitter may put it on the clock pin you want, while on others it doesn't. (I doubt it's a regular I/O pin, because it would be more unlikely that it picks the correct pin so often)

4) If you're using the Microtronix DDR2 core, I believe it works from a script and more off of placement constraints then timing constraints. They assign the FF locations, the delay chain settings, and everything should work. I had a case with this core where the clkctrl global buffer was jumping around, and occasionally would be placed in a bad location and fail timing. Look at the I/O timing(which was unconstrained), and see if it gives vastly different values between the compile that works and the one that doesn't.

Hopefully this points you in the right direction. You need to debug exactly what is wrong, and then find why that is occuring in the bad builds.