Piplining, what is the best way?

Your design has two clocks and Ax is being used in both. This means that Ax is crossing clock domains at least once and you're not taking care of that.

You should use synchronizer chains to synchronize Ax to the proper clock domains.

You may also need synchronizer chains for the outputs.

http://www.altera.com/literature/wp/wp-01082-quartus-ii-metastability.pdf

Otherwise, you're only doing a 16x16 bit multiplication every clock cycle. That's as fast as it can get.

Regarding the "<=" vs "=" issue, it's simple.

With "<=" you always read the value that was present before the event (clock edge, in this case).

With "=", you read the last value you assigned to the signal in the processing block.

If you don't read a signal after doing the assignment, then the behavior is the same.

Thus, the following three code snippets have the same behavior.

always @ (posedge clk) begin

a = b;

b = c;

end

always @ (posedge clk) begin

a <= b;

b <= c;

end

always @ (posedge clk) begin

b <= c;

a <= b;

end

On the other hand, the next code snippet DOES NOT have the same behavior as the other three.

always @ (posedge clk) begin

b = c;

a = b;

end