Pin problem about tri_state_bridge_0_avalon_slave

Hello,

I am new useing the DE2 EP2C35 borad with Quartus II 5.1 Web Edition Full. I use Cypress CY7C1380C SSRAM which requires Avalon Tristate Bridge. After compiling the system,in the project.vhd there are the following informations.

-- the_tri_state_bridge_0_avalon_slave

signal adsc_n_to_the_ssram_0 : OUT STD_LOGIC;

signal bwe_n_to_the_ssram_0 : OUT STD_LOGIC;

signal chipenable1_n_to_the_ssram_0 : OUT STD_LOGIC;

signal outputenable_n_to_the_ssram_0 : OUT STD_LOGIC;

signal tri_state_bridge_0_address : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);

signal tri_state_bridge_0_byteenablen : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);

signal tri_state_bridge_0_data : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)

I do not know how to assign the pins? I couldn't find the matching in the DE2_pin_assignments.Thank you very much for your help!