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Altera_Forum's avatar
Altera_Forum
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10 years ago

output constant signal to oscilloscope

I need to generate a constant high signal to output to an oscilloscope. I tried letting the an signal pulse_out <='1' and this didn't work either. I believe due to my knowledge that an output por...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

--- Quote Start ---

use assign statement: http://www.asic-world.com/verilog/synthesis3.html

this isn't clocked in an always block.

Thus:

assign output = 1'b1;

--- Quote End ---

The op is asking for vhdl, not verilog.

To the op. Assigning something to'1' should work just fine. You don't need a clock. What board are you using. Are you sure its not a problem of where you are probing?