Forum Discussion
Altera_Forum
Honored Contributor
10 years agouse assign statement: http://www.asic-world.com/verilog/synthesis3.html
this isn't clocked in an always block. Thus: assign output = 1'b1;use assign statement: http://www.asic-world.com/verilog/synthesis3.html
this isn't clocked in an always block. Thus: assign output = 1'b1;