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Altera_Forum's avatar
Altera_Forum
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11 years ago

Optimized MOD function?

Hi - I know I can use a divider to do a MOD function, but the latency of the dividers I'm familiar with is 1b/tick, and I'd like something faster. Has anyone written any optimized RTL for doing a MOD function? Thanks /j (Verilog or VHDL is fine).

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    The divider core is probably as optimised as you'll get.

    Why do you need "faster"? Just set the divider core pipeline to less clocks.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I'm interested in latency, not throughput. As it turns out, you can do a parallel Mod function (order log(n) rather than order n) with some clever comparison logic.

    best

    /j