Forum Discussion
Thanks for the response @HRZ . Too bad someone from Intel won't weigh in on host channel vs host pipe convention!!
I assumed they must be the same, and was able to compile and use the example targeting the host_ch BSP on the A10 GX eval card. I was also able to make some modifications to the example and use the one-at-a-time clWritePipeIntelFPGA and clReadPipeIntelFPGA calls. I had not used the clGetExtensionFunctionAddress call or have much experience with function pointers, but seems to work.
Out of curiosity since so few people are using these features - have you tested the throughput you can achieve using the host pipes? I'm considering creating a multi-threaded host application that writes/reads to a device kernel doing some simple data manipulation. I assume any bottleneck would be in the host application or host pipe logic in the BSP - not in the kernel or PCIe interfaces. I'm hoping to move ~1GB/sec