OpenCL Host Channel or Host Pipes

The replies in those threads were made by me (in the old Altera forum). I generally use the terms "pipe" and "channel" interchangeably but I am not sure if Altera/Intel agrees with this. 😅

Either way, the example you posted seems to include everything required to use host channels (or pipes 😜). No low-level DMA access is required; you just need to define the host channel as an argument in the kernel and then write data to it in the host code and read it in the kernel code (or vise versa) using the specific notation used in that example. I believe there is also fine-grained stalling mechanism in-place (similar to on-chip channels), that will block the host if the channel is full or block the kernel if it is empty. There is also an example in "Intel FPGA SDK for OpenCL Pro Edition, Section 5.5.6.4. Example Use of the cl_intel_fpga_host_pipe Extension".