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Altera_Forum
Honored Contributor
Honored ContributorOpenCL HDL co-design on Stratix V
Hi,
Can OpenCL and HDL flow co-exists? Some part of design needs to be in HDL (For through-put optimization) and some part of design needs to be in OpenCL (For Faster development). Finally both the designs needs to be programmed into signal FPGA. Thanks in Advance!3 Replies
Altera_ForumHi,
You need customized OpenCL BSP which contain your fix part of design. To implement that require classic FPGA design flow/skills. There is quite good documentation referring to creating custom BSP at Altera website - e.g. ug_aocl_s5_net_platform.pdf or search for "opencl reference platform porting guide". Jan- Altera_Forum--- Quote Start --- Hi, You need customized OpenCL BSP which contain your fix part of design. To implement that require classic FPGA design flow/skills. There is quite good documentation referring to creating custom BSP at Altera website - e.g. ug_aocl_s5_net_platform.pdf or search for "opencl reference platform porting guide". Jan --- Quote End --- Not anymore! Fellow Geeks, Christmas has come early! Behold, Quartus 16 features! https://documentation.altera.com/#/00015315-aa$aa00107912 Of course, we will still need our board vendor to provide us with Quartus 16 BSPs.
- Altera_Forum
Hi Jan, monstrumus,
Thanks for the quick reply! To summarize, OpenCL library can be created using RTL code (Verilog / VHDL), then include this library file & use the function inside OpenCl kernel. Is there any benchmark for comparing performance of HDL Vs OpenCL implementations? Regards, Ritesh
