Observing CPLD pins

The only limitation with JTAG tools is, since they serially load data in and out, they can't keep up with most "live" clock rates. If your rate is slow, or you're able to step your design and get the same results, then it's a great tool. SignalTap works at system speed because it dumps all the signals you're monitoring directly into RAM, in a parallel manner. Of course, CPLDs don't have RAM, so that's why they don't support SignalTap. You could bring signals to a Logic Analyzer, but most CPLD designs are pretty I/O limited. If you have a "slower" system, you might be able to time-multiplex multiple signals out, but you're probably not going to be able to do the whole chip. You might be able to tap the pins directly to a logic analyzer, depending on if the package is accessible, signal integrity, etc.