Hi Syntax,
I sent a service request a couple of weeks ago and got the following reply.
"The design files used in demo of Quartus II Interactive Tutorial is not provided with the installation of Quartus II software. Quartus II Interactive Tutorial does not serve to provide a laboratory type of hand on or practice as the Interactive Tutorial itself does provide you interactive kind of practice in “Guide Me” and “Test Me” for each module. The ram.vhd that was used in the interactive tutorial is actually a dual-port ram which can be created easily by using MegaWizardPlug-In Maganer. Well, I have attached herewith the ram.vhd per your request. Enjoy the training, thank you."
The original reply did not have the file attached so I had to request it to be resent. I've purposely left out the name of the person who made the reply.
The contents of the ram.vhd file I received was as follows
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.0 Internal Build 207 04/21/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
wren : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END ram;
ARCHITECTURE SYN OF ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_b : STRING;
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
init_file => "ram.hex",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 32,
numwords_b => 32,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => 5,
widthad_b => 5,
width_a => 16,
width_b => 16,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => wraddress,
address_b => rdaddress,
data_a => data,
q_b => sub_wire0
);
END SYN;
As was said in the response, this is a wizard generated file, however it looks nothing like the bits of the file as seen in the tutorial. I've also tried to recreate both the one in the tutorial and the code in the reply using the wizard but have yet to work out which symbol was used for either.
Before receiving the file I had written what I thought was the ram.vhd file from what I saw in the tutorial which was much simpler code and resulted in a symbol that appeared graphically and functionally correct. When I progressed further into the tutorial however I received timing errors compared to the example. Due to my current work load I have not had time to pursue this any further at this stage.
Unfortunately I have to say that I have found it some what disconcerting to try to follow a turtorial that is incomplete and at this stage and I just can't be sure if the errors I'm getting are from something I'm doing wrong or whether the tutorial has problems. I've also found a recurring bug which sometimes causes .bdf files not to paint properly necessatating me to reboot my notebook. I'm not sure whether this is a problem with the software, my notebook or Vista but it's all just a bit too frustrating for me at the moment due to my other commitments.
Anyhow, following is the code I created so see how you go and if you have any better luck than I've had, please let me know.
thanks
Sward
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ram IS
PORT
(
clock: IN std_logic;
data: IN std_logic_vector (15 DOWNTO 0);
wraddress: IN integer RANGE 0 to 31;
rdaddress: IN integer RANGE 0 to 31;
wren: IN std_logic;
q: OUT std_logic_vector (15 DOWNTO 0)
);
END ram;
ARCHITECTURE rtl OF ram IS
TYPE mem IS ARRAY(0 TO 31) OF std_logic_vector(15 DOWNTO 0);
SIGNAL ram_block : mem;
SIGNAL rdaddress_reg : INTEGER RANGE 0 TO 31;
BEGIN
PROCESS (clock)
BEGIN
IF rising_edge(clock) THEN
IF (wren = '1') THEN
ram_block(wraddress) <= data;
END IF;
q <= ram_block(rdaddress);
END IF;
END PROCESS;
END rtl;
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