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i'm assuming that the signals listed in the port map are not available to the case process?
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Why assume, when you can read a book on VHDL or Google the question? VHDL input ports can be "read" within your VHDL process, VHDL output ports cannot. This means any input to the top-level entity can be used within a select statement.
The concept that you are stuck on is that you are somehow thinking the existence of a port named W, X, Y, or Z, *ALSO* creates a signal (wires) by those names. That is not how it works. In your top-level design you need to create the wires you see in your schematic. You can call them anything you want, but it can make more sense to name them the same as the ports they connect to.
Hint: add 1-bit signals w, x, y, and z. Connect those signals to the w, x, y, and z ports on your mux4bit2to1 component, and then drive the LEDG outputs with those signals.
Cheers,
Dave
Honored Contributor
