New to VHDL, problem with variables/signal?

Thanks Dave, that makes sense to me now, but i think i'm still stuck trying to access the ports defined within a component, I have been playing with this code for several days now, even gutted out the BCD decoder just to see if i can design just the MUX

I got rid of the first error message, but now i get a new error as soon as the compiler enters the case process saying that "W" is used but not defined.

I was able to draw up the schematic, compile and do a quick simulation in 20min :) I think i need to learn a little more of the VHDL basics first

This is the code right before i moved to the schematic version, i wanted to use individual components because i would like to grow this project, the next step i am going to substitute the switch inputs (0-3, 5-8) for a pair of BCD counters.

With this the output of the mux was going to drive the LEDG array, i'm assuming that the signals listed in the port map are not available to the case process? I have tried numerous variations and locations of the signal and variable declarations but it still fails.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY lab1 IS
    PORT (
        SW :   IN STD_LOGIC_VECTOR(9 DOWNTO 0);
        HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6);
        LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
        LEDG : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        S : IN STD_LOGIC --Selector bit
        );
    END lab1;
ARCHITECTURE Behavior OF lab1 IS
    COMPONENT mux4bit2to1
        PORT (
            A, B, C, D : IN STD_LOGIC_VECTOR(0 TO 1); --MUX Inputs
            W, X, Y, Z : OUT STD_LOGIC; --MUX Outputs
            S : IN STD_LOGIC
        );
    END COMPONENT;
    
    BEGIN
    mux1 : mux4bit2to1 port map(
        A(0) => SW(0),
        A(1) => SW(5),
        B(0) => SW(1),
        B(1) => SW(6),
        C(0) => SW(2),
        C(1) => SW(7),
        D(0) => SW(3),
        D(1) => SW(8),
        W  => LEDG(0),
        X  => LEDG(1),
        Y  => LEDG(2),
        Z  => LEDG(3),
        S  => S
    );
    
    muxselect: PROCESS (S)
    BEGIN
        case S is 
            when '0' =>
             W <= A(0);
             X <= B(0);
             Y <= C(0);
             Z <= D(0);
            when '1' =>
             W <= A(1);
             X <= B(1);
             Y <= C(1);
             Z <= D(1);
            when OTHERS =>
             W <= '0';
             X <= '0';
             Y <= '0';
             Z <= '0';
        END CASE;
    END PROCESS;
            
    S  <= SW(9);        
    LEDR <= SW;
END Behavior;

-scott-