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I gave up, with this ended up putting it together in the schematic view, is there a way to see the generated code so i can review Quartus's method? How close was i on the original code?
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You haven't given up, you're just beginning to understand :)
In your schematic you have a 4-bit signal that goes between the mux and BCD decoder. In VHDL, these 4-bits cannot be called ledg(3 downto 0) because that signal would be defined as an "out" port in the top-level entity, and you cannot read "out" ports from within your VHDL, you can only drive outputs. Because of this, you would introduce the internal "signal s : std_logic_vector(3 downto 0)", and you would use s to connect the mux and BCD decode, and to drive the ledg output, i.e., ledg <= s;
Try to modify your original VHDL design to match.
Cheers,
Dave
Honored Contributor
