New to VHDL, problem with variables/signal?

To help you understand your mistake, perform the following;

1. Move muxselect into a component

2. Draw blocks for your low-level components

- Use rectangles for your lower-level components, eg., muxselect, mux4bit2to1, and char7seg, and put the port names inside the rectangles.

3. Draw a rectangle around your low-level components, as your top-level design, and draw wires from the muxselect, mux4bit2to1, and char7seg ports to the top-level ports.

When you've finished drawing that diagram, you will see that there is a connection missing, i.e., your muxsel signal S has no corresponding "wire" in your block diagram. In VHDL you create that internal signal using "signal S : std_logic;" at the beginning of the architecture (where you have the component definitions).

Once you get code that Quartus will synthesize, you can use "Tools->Netlist Viewer->RTL Viewer" and you'll see that Quartus draws you a block diagram :)

Cheers,

Dave