Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

New to VHDL, problem with variables/signal?

I am new to VHDL but trying to learn. I would like to make an alarm clock, i decided to start with a mux, 4bit wide 2 to 1. I am using the DE1 board, for testing i want to conect the mux to the swi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I defined S in the port map, i thought that was how i access variables listed in a component? Do i need to add additional variables to then use them in this switch statement? Can you offer any coding suggestions or maybe a place to look, i have been searching online but i am still confused. I was trying to follow along with the altera labs that were included in the CD but i got lost. I pick up quickly but i just need help getting started.