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Altera_Forum's avatar
Altera_Forum
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11 years ago

New to VHDL, problem with variables/signal?

I am new to VHDL but trying to learn. I would like to make an alarm clock, i decided to start with a mux, 4bit wide 2 to 1. I am using the DE1 board, for testing i want to conect the mux to the swi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

S is a port on the mux4bit2to1 component not a signal in he lab1.

So to answer your question about scopes: The scope of variables are only in processes, and the scope of signals is only in the architecture.

The scope of the in and outputs is only in the entities architecture for reading and writing, and only for "interconnecting" in a "parent" architecture.