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Altera_Forum's avatar
Altera_Forum
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15 years ago

Need some helping testing some VHDL Code

I have a project comming up, and I have some VHDL code that I really want to test. Basically what I have so far... Is that I created a symbol file from quartus, and this gets created with no ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You can write a VHDL testbench. and in it you can write very behavioural VHDL that you cannot synthesise. stuff like this:

signal clock : std_logic := '0';

clock <= not clock after 10 ns; -- 100 MHz clock.

reset <= '1', '0' after 25 ns;

and you can write a process like this: 


process
begin
  x <= "001";
  for i in 1 to N_CLOCKS loop
    wait until rising_edge(clk);
  end loop;
  x <= "010"
  --loop again
  --etc
  wait;
end process;