Need help with VHDL error here

main code has lots of components as below , above errors are associated with component calls in the main alu code.

--LIBRARY USAGE

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_signed.all;

use ieee.numeric_std.all;

--ENTITY OF 64 BIT ARITHMETIC LOGIC UNIT

entity alu_64 is

generic(K :natural:=64) ;

port (input1 :in std_logic_vector(K-1 downto 0) ;

input2 :in std_logic_vector(K-1 downto 0) ;

alu_cont:in std_logic_vector(4 downto 0) ;

clk :in std_logic ;

reset :in std_logic ;

alu_out :out std_logic_vector(K-1 downto 0) ;

alu_rout:out std_logic_vector(K-1 downto 0) ;

flag_reg:out std_logic_vector(4 downto 0)) ;

end alu_64;

--BEHAVIORAL DESIGN ARCHITECTURE OF 64 BIT ARITHMETIC LOGIC UNIT

architecture behavioral of alu_64 is

-----------------------------DECLERARION OF MUTIAL REQUIREMENTS---------------------------------

--Mutual signal declerations

shared variable temp_alu_out :std_logic_vector(K-1 downto 0) ;

shared variable temp_alu_rout:std_logic_vector(K downto 0) ;

shared variable temp_flag_reg:std_logic_vector(4 downto 0) ;

shared variable CF :std_logic ;

shared variable OVF :std_logic ;

shared variable ZF :std_logic ;

shared variable PF :std_logic ;

shared variable SF :std_logic ;

--Mutual function decleration

--Carry Flag function decleration

function C_F(input : std_logic) return std_logic is

begin

if input = '1' then

return '1';

end if;

return '0';

end C_F;

--Overflow Flag function decleration

function OV_F(input : std_logic) return std_logic is

begin

if input = '1' then

return '1';

end if;

return '0';

end OV_F;

--Zero Flag function decleration

function Z_F(input : std_logic_vector) return std_logic is

begin

if input = x"00000000" then

return '1';

end if;

return '0';

end Z_F;

--Parity Flag function decleration

function P_F(input : std_logic_vector) return std_logic is

variable counter:integer:= 0;

begin

for i in 0 to K-1 loop

if(input(i) = '1') then

counter := counter + 1;

end if;

end loop;

if(counter mod 2 = 0) then

return '1';

end if;

return '0';

end P_F;

--Sign Flag function decleration

function S_F(input : std_logic) return std_logic is

begin

if(input = '1') then

return '1';

end if;

return '0';

end S_F;

--------------------------------ARITHMETIC UNIT DECLERARIONS-----------------------------------

--SIGNAL DECLERATIONS

--Signal declerations for ADD_64 (64 bit unsigned adder)

shared variable temp_add_out :std_logic_vector(K-1 downto 0);

shared variable temp_cout :std_logic;

--signal declerations for SADD_64 (64 bit signed adder)

shared variable temp_sadd_out :std_logic_vector(K-1 downto 0);

shared variable temp_scout :std_logic;

--signal declerations for SUB_64 (64 bit unsigned subtracter)

shared variable temp_sub_out :std_logic_vector(K-1 downto 0);

shared variable temp_borrowout :std_logic;

--signal declerations for SSUB_64 (64 bit signed subtracter)

shared variable temp_ssub_out :std_logic_vector(K-1 downto 0);

shared variable temp_sborrowout:std_logic;

--signal declerations for MULT_64(64 bit signed and unsigned multiplier)

shared variable temp_mult_out :std_logic_vector(2*K-65 downto 0);

--signal declerations for DIV_64 (64 bit signed and unsigned divisor)

shared variable temp_quotient :std_logic_vector(K-1 downto 0);

shared variable temp_remainder :std_logic_vector(K downto 0);

--signal declerations for MOD_64 (64 bit signed and unsigned modulator)

shared variable temp_mod_out :std_logic_vector(K downto 0);