Need help capturing the period of a wave form. (Verilog)

I see several things wrong with it.

1) Like sstrell said, "posedge" is spelled wrong.

2) There is no initial values or reset for the pos_length and neg_length registers. While the FPGA will initialize with these zero the simulation will have the values of "x" and "x" plus 1 remains "x".

3) same issues with pos_cntstop and neg_cntstop

3) the sequencing of the high period count and low period count is just not right. Assume that at time 0 in_signal is high, which will allow pos_length to start counting. Also assume pos_cntstop is negated. Because in_signal is not low neg_cntstop will be asserted. As soon as the in_signal goes low, pos_cntstop will be asserted. On the next clock edge neg_length will begin counting, but neg_cntstop is already asserted from the previous high period. Because pos_cntstop and neg_cntstop are both asserted you will clear both the counts and the "stop" bits. Your register total_T will only show half the clock period.

4) There is also a major problem if in_signal is not synchronous to sys_clk. An asynchronous signal applied to the enable of counter is guaranteed to fail.

You would be better off to have a single period counter and count the time between rising edges of in_signal. First, double register "in_signal" to get it into sys_clk domain. Then have one more register: in_signal_sync_dly. The riding edge can be detected from In_signal_sync & !in_signal_sync_dly.

So, it becomes:

always @(posesge sys_clk)begin
   in_signal_sync0    <= in_signal;
   in_signal_sync     <= in_signal_sync0;
   in_signal_sync_dly <= in_signal_sync;
 if (reset) begin
   total_T      <= 32'h0;
   legnth_count <= 32'h0;
  end // of reset
 else begin
   if (in_signal_sync && !in_signal_sync_dly) begin
     total_T      <= legnth_count;
     legnth_count <= 32'h0;
    end
   else begin
      legnth_count <= legnth_count + 32'h1;
    end
  end // of not reset
end  // of always