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Altera_Forum's avatar
Altera_Forum
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9 years ago

Moore Finite State Machine questions (VHDL and C)

Hello, I am having some troubles with my Moore state machine. Is it actually possible to use an internal signal or variable dependancy in a IF-statement during a process? Im using a the next...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Im not quite sure what you want. Your first post implies that you assume the process is executed over some finite time. It's not. Its executed in 0 time. Your state transition occurs on a clock edge, so if the RESETSTATE has a next state assignment to state_B, then it will happen on the next clock edge.