Moore Finite State Machine questions (VHDL and C)

This code snippet has issues:

1. VHDL is NOT a programming language, it is a hardware description language. Treating VHDL like C or any other programming language is doomed to failure. You should be drawing your circuit before you write any VHDL.

2. It is not a synchronous process, so you cannot have a counter in it. A counter is a synchronous logic circuit. Having it in an asynchronous process will cause it to count up in infinitely small amount of time.

3. I highly recomend you do not use variables. They can have behaviour that may work like a programming language but then will make your circuit behave really badly. You should use signals for everything.

4. Where is the process that assigns the next state to the current state?

Why are you using a wave builder? you would be much better served writing a testbench in VHDL as you have far more control.