Forum Discussion
Altera_Forum
Honored Contributor
12 years agoThis looks like a ModelSim bug, although you probably do not want the code written this way anyways. Your real value would be converted to an integer and you would lose precision. You probably meant.
// submodule instantiation
submodule submodule_inst (
.data ($realtobits(a)), // IEEE 754 representation of a double precision floating point number.
.out (out_wire)
);
always @ * begin
tmp <= $bitstoreal(data);
end Note that you can use SystemVerilog to pass a real through a port with the module declaration module submodule(
input real data,
output real out
);But at some point, you need to convert the real value into a bit representation recognized by your design.