Modelsim output error when initial differs from zero

I am writing something in verilog in quartus, and appeared to me something strange, but pretty simple actually

This code increments the address correctly

module counter( input wire clock, input wire reset, output reg [4:0]address);initialbegin address = 5'b0endalways@(posedge clock)begin if(reset) begin address <= 5'b0; end else begin address <= address + 5'b00001; endendendmodulethis, the bits that change become not matter, it happens when I start the output to something other than 0

module counter( input wire clock, input wire reset, output reg [4:0]address);initialbegin address = 5'b11101;endalways@(posedge clock)begin if(reset) begin address <= 5'b0; end else begin address <= address + 5'b00001; endendendmoduleDoes anyone know any way to solve this problem?