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There are a few questions abt altera modelsim i would like to ask.
Some questions abt modelsim:
1. Is altera modelsim starter edition support mix language in design ?
2. Is it support like testbench written in vhdl and design written in verilog?
Some questions Modelsim Wave Window:
1. How does modelsim group the signal into a few set of colour? It is because my design some of the input and output are group into green colour and some of it is white colour.
2. How to save some of the input and output signal?
Library Panel:
1. How to rename the tab below the library panel?Like i cant rename the sim tab. However, sometimes i see a tab named vsim.
thx
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Hi,
you can use only one language in a design ( Verilog or VHDL). A testbench is handle like a designfile. It must be written in the same language.
If you want to change the color :
Select the Signal in the Waveform view -> right mouse click -> choose "Properties" -> View and choose a new color. You can go back to the default by deleting the name of the color.
"How to save some of the input and output signal?" What do you mean ? Storing simulation results ?
Kind regards
GPK
Honored Contributor
