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SivaKona's avatar
SivaKona
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Min Pulse Width 'pcie_refclk' the clock_in of PCIe HIP

Hi I have generated a "Intel L/H Tile Avalon Memory Mapped for PCI Express" on Quartus Prime Version 21.2.0.72. I am consistently seeing below violations in all my builds. Am I missing any cons...
  • SivaKona's avatar
    SivaKona
    4 years ago

    I could root cause this issue to signalTap signal.

    I have added pcie_refclk (input 100MHz clock from IO to PLL of PCIe EP ) to SignalTap while SignalTap Sampling clock was set to pcie_clk(the 250MHz pcie_core_clkout generated by the same PLL)

    Regards

    Siva Kona

SivaKona's avatar
SivaKona
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

I could root cause this issue to signalTap signal.

I have added pcie_refclk (input 100MHz clock from IO to PLL of PCIe EP ) to SignalTap while SignalTap Sampling clock was set to pcie_clk(the 250MHz pcie_core_clkout generated by the same PLL)

Regards

Siva Kona