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Honored Contributor
Honored ContributorMigrating from Quartus II 9.0 Web to Quartus Lite 16.0 with MAX II to MAX 10
All, I have a major attempt. (at least I think so). I am jumping from Quartus II Web up to Quartus Lite 16, and I am wanting to modify my existing MAX II files and migrate them into a MAX 10 device. ...
Altera_ForumHonored Contributor
Honored ContributorThanks for the reply Alex.
Not sure how or what the IP works with PLD designs. I know what IP is, but I haven't seen a good clear definition of how it is tied into PLDs/FPGAs. I just thought that you could "LOCK" the device from being read so that was enough. My design is very simple. Some Logic, a counter(LPM), priority-decoder and encoder, and a 25x16 FIFO(LPM). I was going to change the FIFO to a 73X64, which is too big for the current MAX-II and was wanting to see if I could get it to fit into the MAX-10 device. Also wanted to keep it in a simple package that I can solder/breadboard myself. The EQFP package is easy for my to work with, but a BGA is not.... Anyway, thanks for your support. Keith
