Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThanks for the reply Alex.
Not sure how or what the IP works with PLD designs. I know what IP is, but I haven't seen a good clear definition of how it is tied into PLDs/FPGAs. I just thought that you could "LOCK" the device from being read so that was enough. My design is very simple. Some Logic, a counter(LPM), priority-decoder and encoder, and a 25x16 FIFO(LPM). I was going to change the FIFO to a 73X64, which is too big for the current MAX-II and was wanting to see if I could get it to fit into the MAX-10 device. Also wanted to keep it in a simple package that I can solder/breadboard myself. The EQFP package is easy for my to work with, but a BGA is not.... Anyway, thanks for your support. Keith