manual interconnect manipulation

Hi all,

I'm trying to attempt some experiments with SEUs.

Is it possible to change the state of interconnects in altera devices using quartus?

Basically, if a random bit-flip were to occur on an interconnect switch, my solution would catch this error in a clock cycle. In order to prove this, I need to be able to generate random bit-flips via simulation. Is this possible?

I've been looking at Chip Planner and the ECOs, but it seems like "atoms" do not interact with the LAB interconnects.

Can someone please confirm or deny this?