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Altera_Forum
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15 years ago

Making an FIR filter work correctly ...

i'm using the following components from altera:

- altera DSP Development Kit Stratix III Edition with a EP3SL150N board

- Stratix III EP3SL150F1152N FPGA

- HSMC with 2x 14-Bit DAC and 2x 14-Bit ADC

- Quartus II 8.0 wich SP1 (subscription edition / academic)

i'm using the following measurement equipment:

- Tektronix AFG3101 signal generator (one channel)

- Agilent InfiniiVision DSO7012A Oscilloscope (two channels)

- mRS mini VNA vector network analyzer

- mini circuits SLP-50+ alias filter (at DAC output)

The attached .zip-file contains all information about my project, including measurement results and an archive file of the complete project.

I have the following problem: my goal is to have the filter working correctly, allowing input / output voltages up to approx. 2V. Currently, the signal is deviated inside the filter and becomes useless. I've tried many things regarding "signed" and "unsigned" representations, but still hve not found a combination that works - or is the problem located somewhere else?

I desperately need help - I'm walking trough a horrible hell of try and error for about 4 weeks now ... :confused::confused::confused:

remark: The filter curve is a measured attenuation of a house installation in the broadband powerline frequency band.

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