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Altera_Forum's avatar
Altera_Forum
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15 years ago

long time simulation

i wrote a programe in about 600 line using VHDL,there is no errores, but in reports, there is no number of elements(number of logic elements = 0%), how it can be??!! can give a help?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

thx for reply :)

im using QuartusII

but in my packages, there is an looping, without process.

it is correct?

how can i controlling my loops and IF clauses in packages, to use them at main programe's entity?