Issues with output of register values

I am trying to create a chip that takes 512 bit data through the data bus, process that and produces a 512 bit data.

I am having issues with outputting the processed data through the output pins. For now, Roughly system consists of two verilog files which are say process.v and testbench.v

Issue is that whenever I try to output the processed data[saved in reg variables] the Altera Quartus gets stuck on the compilation process[no errors]. The process file consists of the following format

module Process(input clk, input startInput, input getResult, input [31:0] ip1,input [31:0] ip2,output reg [31:0] op1)

reg [31:0] input1 [15:0],

reg [31 : 0] input2 [15:0],

reg [31 to 0] temp [15:0]

always at (posedge clk) begin

initialize and read ip1, ip2 value from testbench on startInput and store to input1 and input2

process: temp = input1[] + input2[]//loop

output op1[] = temp[] // step 3, loop

end

Now, system takes forever to finish the compilation process when I add step3. If I say op1[0] = 32'h0, compilation process goes smoothly. Not sure why that would be the case. I would like the data to be read by a databus from the output pins.

Sorry for the long question..Im lost and any suggestions would be helpful.