IO SStandards in Cyclone IV

The timing isn't big issue in this particular design, but size is an issue. I have large amount of IO signals which have to be connected to connector, while the logic level for external signals may vary from 1.2V to 3.3V, determined by VDDREF analog input which is sample of the external card IOVCC.

The initial drive for this question was a need to avoid many of 2-supply logic level translators. The FPGA is built to operate in the multi-volt supply environment, but the actual logic levels for each io-bamk should be known and assigned in Quartus. But in this case these logic levels are unknown, and re-loading the FPGA with few different bitstreams isn't an option.

So you telling that if i'll assign in Quartus the IO to 3.3 LVCMOS, the inputs treshold values arn't absolute value (3.3V/2) but it always would be approximately VCCIO/2 for the whole voltage range? Even if the VCCIO is as low as 1.2V?

I guess that the 3.3 LVTTL assignment changing the treshold value to little bit lower than 50%?