Honored Contributor
Honored ContributorIt is possible to use the PLL, but you would have to reconfigure it to different frequencies(which then have a range of operation they will lock at, so these need to intersect). This would also require some sort of way to determine the input frequency. It would be a complete pain and I would avoid doing it to. (I have seen it done many, many years ago)
Are you doing DDR or Single Data Rate? By that is the data 480Mbps or 960Mbps? The former will be tough, the latter will be impossible. Also, are you sending edge-aligned or center-aligned? (If it's SDR, then the beauty is you can do edge or center just by inverting the clock, which is basically free). What are the different skews you're trying to match? You have access to the IO delay chain and that's it, which isn't very much and is not PVT calibrated. If it's SDR you can pull the register out of the IO cell and use internal delays. You're not going to get exact delays, but might get close enough. I would say timing constraints are required, as they'll analyze across PVT, account for On-Die Variation, etc. You really can't do all this by hand, and it will show you the window you're working with.