Honored Contributor
Honored ContributorDear Rysc,
Thank you very much for your efforts in writing the 2 articles. My case is different in 2 ways. 1. The constraints we apply will drive Quartus to adjust the clock delay (in PLL) to meet setup/hold at the external register. Firstly, in my design there is one clock which has to align with 3 different data lines (each of which have different board trace lengths). 2. Secondly, I have one more constraint that the clock can vary from 3 MHz to 480 MHz based on user selection. If I use PLL for adjusting the delays, I need to specify the correct clock frequency, which is not possible in my case. In other words, I can't use PLL. Can you please suggest a way out. thanks and regards, rajesh --- Quote Start --- I would recommend timing constraint. Take a look here: http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest It's really long, but if you look at the Getting Started and then use Case 3 or Case 4 of the Explicit Clock Shift MEthod, you should be able to do it pretty quickly. If the delay chain only has two settings(I don't remember), then you're not going to be able to dial them in exact, and it's up to timing constraints to see where you're at. --- Quote End ---