Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi,
In the PCB, on my data and clock lines I have different trace lengths. I want to correct for this offset. There are 3 data lines and 1 clock line. Each of these traces have different lengths. I want that all these lines should have the same delay when they come out of the board. This is a source synchronous interface. regards, rajesh --- Quote Start --- Hi, Can you provide more details of your design? Why do you need to implement this delay? By how much you want to delay signal? Why are you using ALTIOBUF? What signal you want to delay? Is it synchronous or asyncronous? Maybe you are entereing invalid values? "Delay from output register to output pin" option has only two valid values 0 and 1. See Cyclone IV datasheet Table 1–42 and Table 1–43. --- Quote End ---