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Altera_Forum's avatar
Altera_Forum
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17 years ago

Internal generated clock muxing

Hi all, since I used quartus I still have the same problem in all kind of design.

The problem is the following:

When I syntethize an internal clock from another one all time I've been reported false path because the Quartus think that my output clock MUST be faster as my input one.

Example:

I've a clock data recovery machine that oversample my data at 40MHz in order to generate an internal 10MHz signal that is centered with the trasmitted data.

I've moreover 2 different channel of data in which I've to do this thing and I've a logic that select one of the 2 channel in order to be processed.

Quartus all time wanna examinate my paths with the 40MHz, moreover I've a Mux with the 2 clock and ofc it introduces delay. After the Mux I've a clk_control block that redirect it on a regional clock.

I've tried to cut the path (that is the only solution that work), but I wanna that my data will be analyzed with the correct clock (the output of the mux). Can I do something else?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Even though a logic-driven clock might be necessary for your application, you still need to be aware of the things discussed at http://www.alteraforum.com/forum/showthread.php?t=2388.

    If you are using the Classic Timing Analyzer, then I strongly urge you to change to TimeQuest. TimeQuest has much better support for clock muxes and other clock structures that are difficult or impossible to constrain and analyze as you'd want with the Classic Timing Analyzer.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    After the Mux I've a clk_control block that redirect it on a regional clock.

    --- Quote End ---

    If the clock control block in your device family supports clock muxes, then implement the mux inside the clock control block with altclkctrl. Compared to doing the mux portion in logic resources, the clock control block will have less of a problem with things like duty cycle distortion. (See "Advantages of clock control blocks" in post# 7 at http://www.alteraforum.com/forum/showthread.php?t=2388.)
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thx you Brad for the fast answer, I read theese topic now.

    In my last project I could use clk_mux maybe (I'll check it now), whereas in the past I cannot do it and the only solution was cutting the path cause it was a false one.

    I cannot do it in all the desing it seems because quartus need to understand that the 2 signal that enter in the clock mux are clock signals (now I'm trying to set them as clock, previously I used a normal mux and I set its output as a clock signal) but I think I'll see the compilation results tomorrow (more than 1hour of compilation and in 10-15 mins I'll have to go out of office).

    For the idea to switch to Timequest I'll sure wanna do it but I need to do it when we'll start a new project (in which I wanna try also the top down approach with a full incremental compilation).