Forum Discussion
New ContributorIntel PCIe Hard IP Trouble With EFI
Avalon busing appears broken, then you can use the linux 'lspci -vvv' command to verify if the host has correctly set the PCIe endpoint Control register.
As example below, the software driver at host side should set the Memory Space Enable bit[1] and Bus Master bit[2] in Command register to 1.
bit[1] Memory_Space_enable must set (Mem+)
bit[2] Bus_Master must set (BusMater+)
New ContributorYes, it appears that the registers are slightly different when linux hands over the device to my pci driver between the EFI and conventional BIOS bases.
diff efi.txt bios.txt
< Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
---
> Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
3a4
> Latency: 0, Cache Line Size: 64 bytes
I attached the full lspci -vvv -d 1234:0000 dump for both cases.
As you point out the BusMaster flag is not set with EFI booting and also a setting related to caching is not set with EFI.
This is after my linux driver loads, which like I said is failing very badly in the EFI case. I know this isn't a linux driver community and I can take my grips over to the linux e-mail lists, but I don't understand why my driver needs to work differently between BIOS and EFI. Or why bus mastering needs to be turned on even through my design uses no bus mastering.
I'm a bit concerned about the caching flag difference as well.
New ContributorI manually fixed the settings in my pci driver and all in well now.
