Improving the performance of LVDS DDR at 200MHz

C.

I wonder what is at the receiving side? Another FPGA under your control? In that case you could try to constrain those inputs with the obtained results. At 400 MHz you still have an eye of 733 ps and assuming that the PCB layout doesn't add any skew, operation should be possible by fine-tuning the phase of the 'centre-aligned' clock you are sending along. (You actually could lengthen/shorten traces to correct any unbalances due to either FPGA)