Improving the performance of LVDS DDR at 200MHz

You are right Rysc, I am just using DDIO blocks without the altlvds_tx megafunction. So access to the True LVDS circuitry can only be obtained via this megafunction.

I had tried to use the altlvds_tx block before but I had two issues with it.

1) I have a serialising factor of 2. 66 bits down to 33 LVDS channels. This creates my DDR data. However, I require the clock to be centre aligned. There seems to be no option to centre aligned it since by default its edge aligned. I could start rooting about in the megafunction verilog but I am not ready for that yet.

2)When I installed it into my design (did it again today) to check out its performance. Its performance seems to be exactly the same as before, 241ps ODV, setup and hold just the same. It says in the fitter resources that it is not using any dedicated SERDES transmitters. The altlvds_tx is definitely in the code but I think its getting broken down into exactly same circuitry as I have without the SERDES. I read someplace else that at a serialisation factor of 2, the altlvds_tx block just uses the DDIO primitives anyway which would explain what I am seeing.

I seem to be stuck where I can't get access to the true LVDS routing unless I use the altlvds_tx but at a serialisation factor 2 the altlvds_tx doesn't use the dedicated routing :cry:

Yes Rysc it is confusing, very confusing.

Thanks

C