Honored Contributor
Honored ContributorRysc thanks again for taking the time to reply. I appreciate your help.
To answer your questions 1) The board is not laid out at the minute because I am analysing the timing to see if its going to work. The reason I am not using True LVDS is that I am trying to get in to a 780pin stratix 3. With 33 LVDS channels I can't fit all the true LVDS drivers on to one side ( the other sides are going to be used for other interfaces memory etc..). I can't use a mixture either because the skew between a true LVDS driver and emulated driver makes timing difficult. 2) I understand your point about the 'report skew'. For actual timing I always use setup and hold analysis. I used the 'report skew' command in this case because it is easy to spilt out the ODV from everything else. I have produced another version of my test design using True LVDS drivers inside a EP3SE110F1152C3 device. When I put it through Timequest, my setup and hold slack was worse by around 20ps each. The ODV was 23ps more (now 241ps) than the emulated case (218ps). Just to note as well the picture that I posted a few messages back showed the timequest result of the true LVDS case instead of the emulated case. I have reposted both results to this message , sorry :(. When I comb throught the fitter resources used, I see that in the true LVDS case, no regional clocks are being used, only globals. The emulated case is the same. From what Rysc was saying, the true LVDS case should be using a low skew regional clock. Any ideas why the true LVDS case isn't doing that? All my design contains is the DDIO blocks. My input reference clock for the PLL is on the same side as the LVDS signals and it is going in through a dedicated clock input. :eek:
